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HD61203U
(Dot Matrix Liquid Crystal Graphic Display 64-Channel Common Driver)
Preliminary
Description
The HD61203U is a common signal driver for dot matrix liquid crystal graphic display systems. It generates the timing signals (switch signal to convert LCD waveform to AC, frame synchronous signal) and supplies them to the column driver to control display. It provides 64 driver output lines and the impedance is low enough to drive a large screen. As the HD61203U is produced by a CMOS process, it is fit for use in portable battery-driven equipment utilizing the liquid crystal display's low power consumption. The user can easily construct a dot matrix liquid crystal graphic display system by combining the HD61203U and the column (segment) driver HD61202U.
Features
* * * * * Dot matrix liquid crystal graphic display common driver with low impedance Low impedance: 1.5 k max Internal liquid crystal display driver circuit: 64 circuits Internal dynamic display timing generator circuit Display duty cycle When used with the column driver HD61202U: 1/48, 1/64, 1/96, 1/128 When used with the controller HD61830: Selectable out of 1/32 to 1/128 Low power dissipation: During displays: 5 mW Power supplies: VCC: 2.7~5.5V Power supply voltage for liquid crystal display drive: 8V to 16V CMOS process 100-pin plastic QFP, 100-pin plastic TQFP, chip
* * * * *
849
HD61203U
Ordering Information
Type No. HD61203UFS HD61203UTE HCD61203U Package 100-pin plastic QFP (FP-100A) 100-pin thin plastic QFP (TFP-100B) Chip
850
HD61203U
Pin Arrangement
X23 X24 X25 X26 X27 X28 X29 X30 X31 X32 X33 X34 X35 X36 X37 X38 X39 X40 X41 X42 X22 X21 X20 X19 X18 X17 X16 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 VEE V6L V5L V2L V1L VCC DL FS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
HD61203UFS (FP-100A)
DS1 DS2 C NC R NC CR STB SHL GND NC M/S o2 o1 NC FRM M NC FCS DR
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
X43 X44 X45 X46 X47 X48 X49 X50 X51 X52 X53 X54 X55 X56 X57 X58 X59 X60 X61 X62 X63 X64 VEE V6R V5R V2R V1R TH CL2 CL1
(Top view)
851
HD61203U
X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 X32 X33 X34 X35 X36 X37 X38 X39 X40 X41 X42 X43 X44 X19 X18 X17 X16 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 VEE V6L V5L V2L V1L VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
HD61203UTFIA (TFP-100B)
852
DL FS DS1 DS2 C NC R NC CR STB SHL GND NC M/S o2 o1 NC FRM M NC FCS DR CL1 CL2 TH
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
X45 X46 X47 X48 X49 X50 X51 X52 X53 X54 X55 X56 X57 X58 X59 X60 X61 X62 X63 X64 VEE V6R V5R V2R V1R
(Top view)
HD61203U
Pad Arrangement
No.1 NO.79
NO.2
NO.78
Chip Size Coordinate Origin
: 3.40 x 4.08 m2 : Pad Center : Chip center : 90 x 90 m2
NO.28
TYPE CODE HD61203U
NO.54
Pad Size
No.29
No.52
Pad Location Coordinates
PAD PAD No. Name 1 X22 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 X21 X20 X19 X18 X17 X16 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 VEE1 V6L V5L V2L V1L VCC DL FS DS1 DS2 C X Coordinate Y 1853 1712 1544 1385 1238 1091 952 822 692 562 432 302 172 42 -88 -218 -349 -479 -609 -739 -869 -999 -1129 -1259 -1389 -1527 -1665 -1821 -1853 -1853 -1828 -1828 -1828 PAD No. 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 V1R V2R V5R V6R VEE2 X64 X63 X62 X61 X60 X59 X58 X57 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 -1522 -1374 -1236 -1097 -967 -837 -707 -577 -447 -317 -187 -57 73 CL2 1407 -1828 FCS DR 715 853 -1828 -1828 M/S PHI2 PHI1 FRM M 65 195 325 455 585 -1828 -1828 -1828 -1828 -1828 SHL GND -196 -65 -1828 -1828 CR -456 -1828 R -586 -1828 PAD Name Coordinate X Y PAD No. 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 PAD Name X56 X55 X54 X53 X52 X51 X50 X49 X48 X47 X46 X45 X44 X43 X42 X41 X40 X39 X38 X37 X36 X35 X34 X33 X32 X31 X30 X29 X28 X27 X26 X25 X24 X23 X Coordinate Y 203 333 463 593 723 853 983 1122 1261 1399 1546 1693 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853
-1479 -1513 -1513 -1513 -1513 -1513 -1513 -1513 -1513 -1513 -1513 -1513 -1513 -1513 -1513 -1513 -1513 -1513 -1513 -1513 -1513 -1513 -1513 -1513 -1513 -1513 -1513 -1513 -1375 -1213 -976 -846 -716
1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1470 1304 1170 1040 910 779 649 519 389 259 129 -1 -131 -261 -391 -521 -651 -781 -911 -1041 -1171 -1301
853
854
V2L V6L V1L V5L X1 X2 64 output terminals X62 X63 X64 V1R V5R V2R V6R VCC GND VEE Liquid crystal display driver circuits CL1 TH DL 1 Logic 2 Bidirectional shift register 62 63 64 Logic DR SHL STB Oscillator Timing generation circuit Logic R CR C M/S FS DS1 DS2 o1 o2 R f Cf Logic FCS M CL2 FRM
HD61203U
Block Diagram
HD61203U
Block Functions
Oscillator The CR oscillator generates display timing signals and operating clocks for the HD61202U. It is required when the HD61203U is used with the HD61202U. An oscillation resister Rf and an oscillation capacitor Cf are attached as shown in Figure 1. When using an external clock, input the clock into terminal CR and don't connect any lines to terminals R and C. The oscillator is not required when the HD61203U is used with the HD61830. Then, connect terminal CR to the high level and don't connect any lines to terminals R and C (Figure 2).
R
CR
C
R Open
CR
C
Rf
Cf
External Open clock
Figure 1 Oscillator Connection with HD61202U
R Open
CR VCC
C Open
Figure 2 Oscillator Connection with HD61830
855
HD61203U
Timing Generator Circuit The timing generator circuit generates display timing and operating clock for the HD61202U. This circuit is required when the HD61203U is used with the HD61202U. Connect terminal M/S to high level (master mode). It is not necessary when the display timing signal is supplied from other circuits, for example, from HD61830. In this case connect the terminals FS, DS1, and DS2 to high level and M/S to low level (slave mode). Bidirectional Shift Register A 64-bit bidirectional shift register. The data is shifted from DL to DR when SHL is at high level and from DR to DL when SHL is at low level. In this case, CL2 is used as shift clock. The lowest order bit of the bidirectional shift register, which is on the DL side, corresponds to X1 and the highest order bit on the DR side corresponds to X64. Liquid Crystal Display Driver Circuit The combination of the data from the shift register with the M signal allows one of the four liquid crystal display driver levels V1, V2, V5 and V6 to be transferred to the output terminals (Table 1). Table 1 Output Levels
M 1 1 0 0 Output Level V2 V6 V1 V5
Data from the Shift Register 1 0 1 0
856
HD61203U
HD61203U Terminal Functions
Terminal Name VCC GND VEE V1L, V2L V5L, V6L V1R, V2R V5R, V6R Number of Terminals 1 1 2 8 I/O Connected to Power supply Functions VCC-GND: Power supply for internal logic. VCC-VEE: Power supply for driver circuit logic. Power supply Liquid crystal display driver level power supply. V1L (V1R), V2L (V2R): Selected level V5L (V5R), V6L (V6R): Non-selected level Voltages of the level power supplies connected to V1L and V1R should be the same. (This applies to the combination of V2L & V2R, V5L & V5R and V6L & V6R respectively.) 1 I VCC or GND Selects master/slave. * M/S = VCC: Master mode When the HD61203U is used with the HD61202U, timing generation circuit operates to supply display timing signals and operation clock to the HD61202U. Each of I/O common terminals DL, DR, CL2, and M is in the output state. M/S = GND: Slave mode The timing operation circuit stops operating. The HD61203U is used in this mode when combined with the HD61830. Even if combined with the HD61202U, this mode is used when display timing signals (M, data, CL2, etc.) are supplied by another HD61203U in the master mode. Terminals M and CL2 are in the input state.
M/S
*
When SHL is VCC, DL is in the input state and DR is in the output state. When SHL is GND, DL is in the output state and DR is in the input state. FCS 1 I VCC or GND Selects shift clock phase. * FCS = VCC Shift register operates at the rising edge of CL2. Select this condition when HD61203U is used with HD61202U or when MA of the HD61830 connects to CL2 in combination with the HD61830. FCS = GND Shift register operates at the fall of CL2. Select this condition when CL1 of HD61830 connects to CL2 in combination with the HD61830.
*
857
HD61203U
Terminal Name FS Number of Terminals 1 I/O I Connected to Functions VCC or GND Selects frequency. When the frame frequency is 70 Hz, the oscillation frequency should be: fOSC = 430 kHz at FCS = VCC fOSC = 215 kHz at FCS = GND This terminal is active only in the master mode. Connect it to VCC in the slave mode. DS1, DS2 2 I VCC or GND Selects display duty factor. Display Duty Factor DS1 DS2 1/48 GND GND 1/64 GND VCC 1/96 VCC GND 1/128 VCC VCC
These terminals are valid only in the master mode. Connect them to VCC in the slave mode.
$%
TH CL1 CR, R, C
1 1 1 3
I
VCC or GND
Input terminal for testing Connect to $% VCC. Connect TH and CL1 to GND. Oscillator In the master mode, use these terminals as shown below:
Internal oscillation Rf R CR Cf C External clock Open R External clock CR Open C
In the slave mode, stop the oscillator as shown below:
Open R VCC CR Open C
o1, o2
2
O
HD61202U
Operating clock output terminals for the HD61202U * Master mode Connect these terminals to terminals o1 and o2 of the HD61202U respectively. Slave mode Don't connect any lines to these terminals.
*
858
HD61203U
Terminal Name FRM Number of Terminals 1 I/O O Connected to Functions HD61202U Frame signal * Master mode Connect this terminal to terminal FRM of the HD61202U. Slave mode Don't connect any lines to this terminal.
* M 1 I/O
MB of Signal to convert LCD driver signal into AC HD61830 or M * Master mode: Output terminal of HD61202U Connect this terminal to terminal M of the HD61202U. * Slave mode: Input terminal Connect this terminal to terminal MB of the HD61830. Master mode: Output terminal Connect this terminal to terminal CL of the HD61202U. Slave mode: Input terminal Connect this terminal to terminal CL1 or MA of the HD61830.
CL2
1
I/O
CL1 or MA of HD61830 or CL of HD61202U
Shift clock *
*
DL, DR
2
I/O
Open or FLM of HD61830
Data I/O terminals of bidirectional shift register DL corresponds to X1's side and DR to X64's side. * Master mode Output common scanning signal. Don't connect any lines to these terminals normally. Slave mode Connect terminal FLM of the HD61830 to DL (when SHL = VCC) or DR (when SHL = GND). VCC VCC Output Output GND Output Output VCC Input Output GND GND Output Input
*
M/S SHL DL DR NC SHL 5 1 I Open VCC or GND Not used.
Don't connect any lines to this terminal. Selects shift direction of bidirectional shift register. SHL VCC GND Shift Direction DL DR DL DR Common Scanning Direction X1 X64 X1 X64
859
HD61203U
Terminal Name X1-X64 Number of Terminals 64 I/O O Connected to Functions Liquid crystal display Liquid crystal display driver output Output one of the four liquid crystal display driver
M 1 0
Data Output level
1
0
1
0
V2 V6 V1 V5
When SHL is VCC, X1 corresponds to COM1 and X64 corresponds to COM64. When SHL is GND, X64 corresponds to COM1 and X1 corresponds to COM64.
860
M/S TH L L L L L H H H H H H -- -- -- -- -- From MB of HD61830 L To DL/DR of HD61203U No. 2 From DL/DR of HD61203U No. 1 -- -- From FLM of HD61830 From MA of HD61830 H From FLM of HD61830 To DL/DR of HD61203U No. 2 -- From FLM of HD61830 L L L H H H H H -- -- -- -- -- From MB of HD61830 From CL1 of HD61830 H From FLM of HD61830 -- COM1-COM64 COM64-COM1 COM1-COM64
CL1 FCS FS
DS1 DS2 STB CR
R
C
o1
o2
FRM
M
CL2
SHL
DL
DR
X1-X64
HD61203U Connection List
Example of Application
A
B
COM64-COM1
C
L
L
L
H
H
H
H
H
H
--
--
--
--
--
From MB of HD61830 L
From MA of HD61830
H
COM65-COM128
From DL/DR COM128-COM65 of HD61203U No. 1 -- -- -- -- COM1-COM64 COM64-COM1
D or L H Cf L Rf Cf H
H
L
L
H
H
L
L
H
Rf
Rf
Cf
To o1 of To o2 of To FRM of To M of HD61202U HD61202U HD61202U HD61202U
To CL of HD61202U
H
E or L H Cf
H
L
L
H
H
L
L
H
Rf
To o1 of To o2 of To FRM of To M of HD61202U HD61202U HD61202U HD61202U HD61203U
To CL of HD61202U To CL2 of HD61203U
--
To DL/DR COM1-COM64 of HD61203U No. 2 L To DL/DR of HD61203U No. 2 -- COM64-COM1
F
L
L
L
H
H
H
H
H
H
--
--
--
--
--
From M of HD61203U No. 1
From CL2 of HD61203U No. 1
H
From DL/DR of HD61203U No. 1 L --
--
COM1-COM64
From DL/DR COM64-COM1 of HD61203U No. 1
Notes: H: VCC L: GND
} Fixed
"--" means "open". Rf: Oscillation resister Cf: Oscillation capacitor
HD61203U
861
HD61203U
Outline of HD61203U System Configuration
Use with HD61830 1. When display duty ratio of LCD is 1/64
HD61830 No. 1 COM1 COM64 LCD One HD61203U drives common signals. Refer to Connection List A.
HD61830 No. 1
LCD COM1 COM64 COM1 COM64 Upper Lower One HD61203U drives common signals for upper and lower panels. Refer to Connection List A.
HD61830 No. 1 LCD COM1 COM64 COM1 COM64 Upper Lower Two HD61203Us drive upper and lower panels separately to ensure the quality of display. No. 1 and No. 2 operate in parallel. For both of No. 1 and No. 2, refer to Connection List A.
No. 2
2. When display duty ratio of LCD is from 1/65 to 1/128
HD61830 No. 1 COM1 COM128 Two HD61203Us connected serially drive common signals. Refer to Connection List B for No. 1. Refer to Connection List C for No. 2.
LCD
No. 2 HD61830 No. 1 LCD COM1 Upper COM128 COM1 Lower COM128 Two HD61203Us connected serially drive upper and lower panels in parallel.
No. 2 HD61830 No. 1
Refer to Connection List B for No. 1. Refer to Connection List C for No. 2.
LCD No. 2 No. 3 COM1 Upper COM128 COM1 Lower COM128 Two sets of HD61203Us connected serially drive upper and lower panels in parallel to ensure the quality of display. Refer to Connection List B for No. 1 and 3. Refer to Connection List C for No. 2 and 4.
No. 4
862
HD61203U
Use with HD61202 (1/64 Duty Ratio)
COM1 COM64 HD61202U HD61202U One HD61203U drives common signals and supplies timing signals to the HD61202Us. Refer to Connection List D.
No. 1
LCD
LCD Upper Lower Refer to Connection One HD61203U drives List D. upper and lower panels and supplies timing signals to the HD61202Us.
COM1 COM64 No. 1 COM1 COM64 HD61202U
HD61202U No. 1 LCD COM1 COM64 COM1 COM64 HD61202U Upper Lower Two HD61203Us drive upper and lower panels in parallel to ensure the quality of display. No. 1 supplies timing signals to No. 2 and the HD61202Us. Refer to Connection List E for No. 1. Refer to Connection List F for No. 2.
No. 2
863
HD61203U
Connection Example 1 Use with HD61202U (RAM Type Segment Driver) 1. 1/64 duty ratio (see Connection List D)
C Cf CR Rf +5V (VCC) R3 V1 R1 R1 R2 R1 R1
- + - + - + - +
X1 (X64)
COM1 LCD panel
R VCC V1L, V1R V6L, V6R
X64 (X1)
COM64
R3 V6 R3 R3 V3 V4 R3 V5 R3 V2 VEE
HD61203U
V5L, V5R V2L, V2R VEE
VCC SHL DS1 DS2 TH CL1 FS M/S FCS STB
-10V 0V
Contrast GND Open Open DL DR
R3 = 15 ( ) is at SHL = Low Note: The values of R1 and R2 vary with the LCD panel used. When bias factor is 1/9, the values of R1 and R2 should satisfy R1 1 = 4R1 + R2 9 For example, R1 = 3 k, R2 = 15 k
Figure 3 Example 1
864
V1 V3 V4 V2 VCC GND VEE
V1L, V1R V3L, V3R V4L, V4R V2L, V2R VCC GND VEE
M CL2 FRM o1 o2
M CL FRM o1 o2
HD61202U
C o2 o1
47 48 49
CL2 DL (DR)
o2
1 2 3
CL2
1
2
3
63
64
1
2
3
63
64
1
FRM
DL (DR) * * DR (DL)
*
*
*
*
M V1 V6 V5
1 frame
1 frame V1 V6 V2
X1 (X64)
V1 V6 V5 V5
X2 (X63)
V6 V2
Figure 4 Example 1 Waveform (RAM Type, 1/64 Duty Cycle)
V6 ( ): at SHL = Low Note: * Phase difference between DL (DR) and CL2
V5
HD61203U
865
HD61203U
Connection Example 2 Use with HD61830 (Display Controller) 1. 1/64 duty ratio (see Connection List A)
Open VCC Open VCC V1 See connection example V6
C CR R VCC V1L, V1R V6L, V6R
X1 (X64)
COM1 LCD panel
X64 (X1)
COM64
HD61203U
V5 V2
V5L, V5R V2L, V2R
M CL2 DL (DR) DR (DL) Open VCC
M CL1 FLM
HD61830 (Display controller)
VEE GND
VEE GND
Open Open Open
FRM o1 o2
SHL DS1 DS2 TH CL1 FS M/S FCS STB
( ) is at SHL = Low
Figure 5 Example 2 (1/64 Duty Ratio)
866
MB 1 frame 1 frame
FLM
From HD61830
1 CL1
2
3
4
64
1
2
3
64
1
X1 (X64) V6 V5
V1 V2
V6
V1
X2 (X63) V6 V5 V5
V1 V6 V2 V6 V5
Figure 6 Example 2 Waveform (1/64 Duty Ratio)
X64 V6 (X1) V5 V2 ( ): at SHL = Low V1 V6
V5 V2
HD61203U
867
HD61203U
2. 1/100 duty ratio (see Connection List B, C)
VCC Open Open VCC See Connection Example 1 V1 V6 VCC V1L, V1R V6L, V6R V5L, V5R V2L, V2R VEE GND R CR C SHL DS1 DS2 TH CL1 FS M/S FCS STB X1 (X64) COM1 X64 (X1) LCD panel COM64 COM65 X1 (X64) COM100 X36 (X29) SHL DS1 DS2 TH CL1 FS M/S FCS STB VCC Note: ( ) is at SHL = Low
VCC
V5 V2
VEE GND
HD61830 Display controller
FLM MA MB
Open VCC Open
C CR R
Figure 7 Example 2 (1/100 Duty Ratio)
868
HD61203U (slave) No. 2
VCC V1L, V1R V6L, V6R V5L, V5R V2L, V2R VEE GND
M CL2 DL (DR) DR (DL)
M CL2 DL (DR) HD61203U (master) No. 1 DR (DL) Open
MB
1 frame 1 frame
HD61830 FLM
MA DR(DL) HD61203U No. 1 X1 (X64) V6 V5 V1 V2 V1 V5 V5
100
1
100
2
3
64
65
66
1
2
3
64
65
66
100
1
2
HD61203U No. 1
V6
V1
X64 (X1) V6
V6 V2 V1 V5
V6 V5
V6 V5 V2 V1 V5
HD61203U No. 2 X1 (X64)
Figure 8 Example 2 Waveform (1/100 Duty Ratio)
X36 (X29) V2 V5 V6 V6
V2
V5
HD61203U
869
HD61203U
Absolute Maximum Ratings
Item Power supply voltage (1) Power supply voltage (2) Terminal voltage (1) Terminal voltage (2) Operating temperature Storage temperature Symbol VCC VEE VT1 VT2 Topr Tstg Limit -0.3 to +7.0 VCC - 17.0 to VCC + 0.3 -0.3 to VCC + 0.3 VEE - 0.3 to VCC + 0.3 -20 to +75 -55 to +125 Unit V V V V C C Notes 2 5 2, 3 4, 5
Notes: 1. If LSIs are used beyond absolute maximum ratings, they may be permanently destroyed. We strongly recommend you to use the LSI within electrical characteristic limits for normal operation, because use beyond these conditions will cause malfunction and poor reliability. 2. Based on GND = 0V. 3. Applies to input terminals (except V1L, V1R, V2L, V2R, V5L, V5R, V6L, and V6R) and I/O terminals at high impedance. 4. Applies to V1L, V1R, V2L, V2R, V5L, V5R, V6L, and V6R. 5. Apply the same value of voltages to V1L and V1R, V2L and V2R, V5L and V5R, V6L and V6R, VEE (23 pin) and VEE (58 pin) respectively. Maintain VCC V1L = V1R V6L = V6R V5L = V5R V2L = V2R VEE
870
HD61203U
Electrical Characteristics
DC Characteristics (VCC = 2.7V to 5.5V, GND = 0V, VCC-VEE = 8.0 to 16.0V, Ta = -20 to +75C)
Specifications Test Item Input high voltage Input low voltage Output high voltage Output low voltage Vi-Xj on resistance Symbol VIH VIL VOH VOL RON Min 0.7 x VCC GND VCC - 0.4 -- -- Typ -- -- -- -- -- Max VCC 0.3 x VCC -- 0.4 1.5 Unit V V V V k IOH = -0.4 mA IOL = 0.4 mA VCC-VEE = 10V Load current 150 A Vin = 0 to VCC Vin = VEE to VCC In master mode external clock operation In slave mode shift register Cf = 20 pF 5% Rf = 47 k 2% In master mode 1/128 duty cycle Cf = 20 pF Rf = 47 k In slave mode 1/128 duty cycle In master mode 1/128 duty cycle Test Conditions Notes 1 1 2 2 13
Input leakage current Input leakage current Operating frequency
IIL1 IIL2 fopr1
-1.0 -2.0 50
-- -- --
1.0 2.0 600
A A kHz
3 4 5
Operating frequency Oscillation frequency
fopr2 fosc
0.5 315 --
-- 450 --
1500 585 1.0
kHz kHz mA
6 7, 12 8, 9
Dissipation current (1) IGG1
Dissipation current (2) IGG2 Dissipation current IEE
-- --
-- --
200 100
A A
8, 10 8, 11
Notes: 1. Applies to input terminals FS, DS1, DS2, CR, SHL, M/S, and FCS and I/O terminals DL, M, DR and CL2 in the input state. 2. Applies to output terminals, o1, o2, and FRM and I/O common terminals DL, M, DR, and CL2 in the output status. 3. Applies to input terminals FS, DS1, DS2, CR, $%, SHL, M/S, FCS, CL1, and TH, I/O terminals DL, M, DR, and CL2 in the input state and NC terminals. 4. Applies to V1L, V1R, V2L, V2R, V5L, V5R, V6L, and V6R. Don't connect any lines to X1 to X64.
871
HD61203U
5. External clock is as follows.
TH External clock waveform 0.7 VCC 0.5 VCC 0.3 VCC trcp External clock CR tfcp Open Open R C TL Duty cycle = TH x 100% TH + TL Max 55 50 50 Unit % ns ns
Min Duty cycle trcp tfcp 45 -- --
Typ 50 -- --
6. Applies to the shift register in the slave mode. For details, refer to AC characteristics. 7. Connect oscillation resistor (Rf) and oscillation capacitance (Cf) as shown in this figure. Oscillation frequency (fOSC) is twice as much as the frequency (fo) at o1 or o2.
Cf Rf CR R C o1, o2
Cf = 20 pF Rf = 47 k
fOSC = 2 x fo
8. No lines are connected to output terminals and current flowing through the input circuit is excluded. This value is specified at VIH = VCC and VIL = GND. 9. This value is specified for current flowing through GND in the following conditions: Internal oscillation circuit is used. Each terminal of DS1, DS2, FS, SHL, M/S, $%, and FCS is connected to VCC and each of CL1 and TH to GND. Oscillator is set as/ described in note 7. 10. This value is specified for current flowing through GND under the following conditions: Each terminals of DS1, DS2, FS, SHL, $%, FCS and CR is connected to VCC, CL1, TH, and M/S to GND and the terminals CL2, M, and DL are respectively connected to terminals CL2, M, and DL of the HD61203U under the condition described in note 9. 11. This value is specified for current flowing through VEE under the condition described in note 9. Don't connect any lines to terminal V. 12. This figure shows a typical relation among oscillation frequency, Rf and Cf. Oscillation frequency may vary with the mounting conditions.
600 fOSC (kHz) Cf = 20 pF 400 200
0
50 Rf (k)
100
872
HD61203U
13. Resistance between terminal X and terminal V (one of V1L, V1R, V2L, V2R, V5L, V5R, V6L, and V6R) when load current flows through one of the terminals X1 to X64. This value is specified under the following conditions:
VCC-VEE = 10V V1L = V1R, V6L = V6R = VCC - 1/7 (VCC-VEE) V2L = V2R, V5L = V5R = VEE + 1/7 (VCC-VEE) RON V1L, V1R V6L, V6R V5L, V5R V2L, V2R Connect one of the lines Terminal X (X1 to X64)
The following is a description of the range of power supply voltage for liquid crystal display drive. Apply positive voltage to V1L = V1R and V6L = V6R and negative voltage to V2L = V2R and V5L = V5R within the AEV range. This range allows stable impedance on driver output (RON). Notice that AEV depends on power supply voltage VCC-VEE.
VCC V1 (V1L = V1R) V V6 (V6L = V6R) 3.5
Range of power supply voltage for liquid crystal display drive
V (V) V V5 (V5L = V5R) V2 (V2L = V2R) VEE
2
8 VCC-VEE (V)
16
Correlation between driver output waveform and power supply voltage for liquid crystal display drive
Correlation between power supply voltage VCC-VEE and V
873
HD61203U
Terminal Configuration
Input Terminal VCC PMOS Applicable terminals: CR, M/S, SHL, FCS, DS1, DS2, FS
NMOS
I/O Terminal VCC (Input circuit) PMOS VCC
Applicable terminals: DL, DR, CL2, M
Enable NMOS PMOS Data NMOS Output circuit (tristate) Output Terminal VCC Applicable terminals: o1, o2, FRM PMOS
NMOS
Output Terminal PMOS VCC PMOS VCC NMOS VEE NMOS VEE V2L, V2R V5L, V5R V6L, V6R V1L, V1R
Applicable terminals: X1 to X64
874
HD61203U
AC Characteristics (VCC = 2.7V to 5.5V, GND = 0V, Ta = -20 to +75C) In the Slave Mode (M/S = GND)
CL2 (FCS = GND) (Shift clock)
0.7 VCC 0.3 VCC tf tr 0.7 VCC 0.3 VCC tDD tDH 0.7 VCC 0.3 VCC tDHW tWLCL2L tr tf tDS tWHCL2H tWHCL2L tWLCL2H
CL2 (FCS = VCC) (Shift clock)
DL (SHL = VCC) DR (SHL = GND) Input data
DR (SHL = VCC) DL (SHL = GND) Output data
0.7 VCC 0.3 VCC
Item CL2 low level width (FCS = GND) CL2 high level width (FCS = GND) CL2 low level width (FCS = VCC) CL2 high level width (FCS = VCC) Data setup time Data hold time Data delay time Data hold time CL2 rise time CL2 fall time
Symbol tWLCL2L tWLCL2H tWHCL2L tWHCL2H tDS tDH tDD tDHW tr tf
Min 450 150 150 450 100 100 -- 10 -- --
Typ -- -- -- -- -- -- -- -- -- --
Max -- -- -- -- -- -- 200 -- 30 30
Unit ns ns ns ns ns ns ns ns ns ns
Note
1
Notes: 1. The following load circuit is connected for specification.
Output terminal 30 pF (includes jig capacitance)
875
HD61203U
2. In the master mode (M/S = VCC, FCS = VCC, Cf = 20 pF, Rf = 47 k)
CL2 0.7 VCC 0.3 VCC tDS DL (SHL = VCC) DR (SHL = GND) tDD DR (SHL = VCC) DL (SHL = GND) tDFRM FRM 0.7 VCC 0.3 VCC tDM 0.7 VCC 0.3 VCC 0.7 VCC 0.3 VCC tDFRM 0.7 VCC 0.3 VCC tDD tDH tDS tDH tWCL2L tWCL2H
M
tf
tr
tWo1H 0.7 VCC
o1 tWo1L o2 tD12 tD21
0.3 VCC
0.7 VCC tWo2H tf tWo2L tr 0.3 VCC
876
HD61203U
Item Data setup time Data hold time Data delay time FRM delay time M delay time CL2 low level width CL2 high level width o1 low level width o2 low level width o1 high level width o2 high level width o1-o2 phase difference o2-o1 phase difference o1, o2 rise time o1, o2 fall time Symbol tDS tDH tDD tDFRM tDM tWCL2L tWCL2H tWo1L tWo2L tWo1H tWo2H tD12 tD21 tr tf Min 20 40 5 -2 -2 35 35 700 700 2100 2100 700 700 -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- +2 +2 -- -- -- -- -- -- -- -- 150 150 Unit s s s s s s s ns ns ns ns ns ns ns ns
877

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